The present invention relates to a capacitor array for use within an analog-to-digital converter. More particularly, the present invention relates to a capacitor array configured to reduce and/or eliminate the non-linearities within an analog-to-digital converter that may be created by the voltage coefficient of the capacitors utilized therewithin.
Resistor networks have been used for sampling methodologies of analog-to-digital converters. Over the past several years, Complementary Metallic Oxide Semiconductor (CMOS) integrated circuit technology is becoming more commonplace with A/D converters in that the CMOS technology is relatively inexpensive and yet versatile in allowing designers to include digital logic circuitry and analog circuitry in the same integrated circuit.
As the requirements for precision have continued to increase with respect to analog-to-digital (A/D) converters, the use of resistor networks for sampling has been substantially reduced due to the difficulty in producing accurate resistors using CMOS technology. Instead, the technique of charge redistribution, which utilizes capacitor networks instead of resistor networks, has become the most commonly used methodology in CMOS analog-to-digital converters. Despite the resulting improvement, the demands on designers for further improvements in the precision for capacitive charge redistribution techniques continues to increase as well.
An exemplary A/D converter which employs capacitive charge redistribution is discussed more fully in U.S. Pat. No. 5,852,415, issued on Dec. 22, 1998 to Cotter et al. The six-bit converter disclosed therein generally comprises an array of binary-weighted capacitors configured with a comparator circuit, together with a series of switches which purport to enable sampling by the A/D converter. In that A/D converter, for example, one switch is configured to connect a common terminal of the capacitors to ground while another series of switches are configured for selectively connecting the other terminal of the capacitors to ground, to an input voltage, Vin, or to a reference voltage, Vref. During operation, that A/D converter samples the input voltage by charging up the capacitor array to the input voltage, Vin, during a sampling step. Next, the A/D converter redistributes this charge on the capacitors to the input of the comparator circuit during a holding step. Finally, during a charge redistribution step, the A/D converter selectively compares the voltage at the comparator circuit to the reference voltage to iteratively derive a digital representation of the analog input voltage, Vin.
Unfortunately, with respect to the Cotter et al. design, as the input voltage changes, the value of the capacitance also changes, thus resulting in non-linearities within the A/D converter. Specifically, the voltage coefficient of capacitance, namely the rate of fractional change in capacitance as a function of the change in voltage, tends to create a non-linear charge on the capacitors within the array. These voltage coefficient non-linearities generally result from, interalia, processing variations in the doping levels of the capacitors during manufacture. Moreover, the size of the depletion regions within the capacitors can be significantly affected depending on manufacturing techniques. Accordingly, these voltage-coefficient non-linearity characteristics can be more problematic to the A/D converter, and particularly those A/D converters which use polypoly-type capacitors.
Some manufacturing approaches directed to reducing the non-linearities resulting from the voltage coefficient of capacitance within A/D converters have employed metal oxide capacitors due to their minimal depletion region and low or essentially non-existent voltage coefficient. However, such capacitors are larger in area, e.g., often 2 or more times larger than low cost, production level, polypoly-type capacitors, and thus require a larger layout area. Further, these metal oxide capacitors can be more difficult to manufacture, such as by requiring additional critical metallurgical steps, and thus can be very expensive to produce.
Other manufacturing approaches directed to reducing the non-linearities resulting from voltage coefficient of capacitors have included the precise controlling and matching of the doping levels on the capacitors in an attempt minimize the depletion region of the involved capacitors. However, such doping techniques can significantly increase the manufacturing costs of the capacitors. Moreover, such doping techniques are not able to reduce the non-linearities within the capacitor array to the standards expected to be required in the future for precision and accuracy in A/D converters, e.g. to errors of less than 1 LSB.
Another approach for minimizing the impact on linearity created by voltage coefficients in capacitors is disclosed more fully in U.S. Pat. No. 4,878,151 issued to Gallichio on Oct. 31, 1989, and which describes an xe2x80x9canti-parallelxe2x80x9d capacitor arrangement having two capacitors connected such that the polarity of one capacitor is connected to the reverse polarity of the other capacitor. Gallichio states that the change in capacitance of each capacitor as the input voltage is varied cancels out the linear variation in the capacitance of each capacitor due to the reverse polarity of the two capacitors.
Further, U.S. Pat. No. 4,918,454, issued on Apr. 17, 1990 to Early et al., discloses that if two capacitors are combined in parallel, one with a negative voltage across and the other with a positive voltage across, the dominant first order coefficient, i.e., the first order coefficient in a Taylor series expansion of the voltage coefficient for a given capacitance, and which corresponds to the dominant non-linearity of the capacitor, can be canceled out. In general, this Taylor series expansion can be expressed as:
C=CNOMINAL+K1V+K2V2+. . .
Thus, in addition to the dominant first order capacitive voltage coefficient, K1, there also exists second order, K2, third order, K1, etc., coefficients which also must be addressed to have a perfectly linear capacitor.
With reference to FIG. 1, a schematic representation of the anti-parallel configuration, and with reference to FIG. 2, a cross-sectional diagram of an anti-parallel configuration, each as disclosed by Early et al. are shown. As shown, Early et al. discloses an anti-parallel configuration in which two capacitors 28 and 30, are directly connected with their polarity reversed with respect to each other to provide a single capacitor component having a low voltage coefficient.
Unfortunately, the implementation of the capacitor component disclosed in Early et al. into an array of capacitors for charge redistribution, with each capacitor component within the array comprising at least two capacitors configured in an xe2x80x9canti-parallelxe2x80x9d manner, i.e., the polarity of each capacitor within the capacitor component alternating from positive to negative, would have its disadvantages. As one will appreciate, such a configuration and interconnection process would require a sizable layout area when producing such an array arrangement. Moreover, such an interconnection process could prove to be quite complicated during manufacture. For example, the requirements for the layout area would be greatly increased due to the need for excess space to provide the interconnections from the top plate of one capacitor to the bottom plate of another adjacent capacitor. Another disadvantage is that an array of capacitor components comprising capacitors successively configured in an anti-parallel manner could introduce coupling effects into the capacitive network of the A/D circuit. These coupling effects, which result from the effects of the plurality of crossing interconnections, would lead to crosstalk, dynamic switching errors, and dc accuracy problems. Accordingly, the manufacturing costs and complexity would be increased for such a capacitor array comprising a plurality of anti-parallel capacitors within an A/D converter.
Accordingly, a need exists for a capacitor array which overcomes the above described problems with prior art A/D converters. In particular, a need exists for a capacitor array configured to reduce and/or eliminate the voltage coefficient non-linearities present within an A/D converter, without complicating the manufacturing and layout requirements for the A/D converter. Further, a need exists for a method for negating the voltage coefficient of the capacitors as used within an A/D converter to facilitate minimal linearity errors of less than 1 LSB.
A capacitor array in accordance with the present invention addresses many of the shortcomings of the prior art. In accordance with one aspect of the present invention, the capacitor array is configured to negate or cancel the influence of the voltage coefficient of the capacitors within the array, and thus reduce and or eliminate the voltage coefficient related non-linearities present within the A/D converter. In accordance with an exemplary embodiment, a first capacitor within the array is suitably configured with at least one additional capacitor in the array such that the charge across the array is linear with respect to an input voltage applied to the input of the array. In addition, the voltage coefficient induced non-linearities from the first capacitor can be suitably canceled by the inverse voltage coefficient induced non-linearities of any additional capacitors within the balance of the array, thereby reducing the potential for non-linearities within the A/D converter.